Features generally required of a PLL (Phase Locked Loop) modulation circuit are low cost, low power consumption, low-noise characteristics, and high modulation accuracy. In order to increase the modulation accuracy of a PLL modulation circuit, it is desirable for the PLL bandwidth to be made a wider band than a modulation signal.
However, when the bandwidth of a PLL modulation circuit is made a wide band, its noise characteristics degrade. There has thus been proposed, as a technology for implementing a wideband PLL modulation circuit, two-point modulation whereby the bandwidth of a PLL modulation circuit is set narrower than the bandwidth of a modulation signal, and modulation within the PLL bandwidth and modulation outside the PLL bandwidth are performed at two different places (see Patent Document 1, for example).
FIG. 1 is a drawing showing a simplified configuration of a conventional wideband PLL modulation circuit. As shown in FIG. 1, conventional PLL modulation circuit 10 is equipped with voltage controlled oscillator (VCO) 11, divider 12, phase comparator 13, and loop filter 14.
Voltage controlled oscillator 11 generates RF modulation signal S12 whose oscillation frequency changes according to control voltage signal S11 applied to a control voltage terminal. Divider 12 divides the frequency of RF modulation signal S12 output from voltage controlled oscillator 11. Phase comparator 13 compares the phase of output signal S13 from divider 12 with the phase of reference signal S14, and outputs output signal S15 in accordance with the phase difference. Loop filter 14 smoothes output signal S15 from phase comparator 13.
Conventional PLL modulation circuit 10 also includes DA converter 15, low-pass filter 16, and adder 17.
Digital baseband modulation signal S16 from outside is supplied to divider 12 and DA converter 15. DA converter 15 performs DA conversion of digital baseband modulation signal S16 and supplies the resulting signal to low-pass filter 16.
Low-pass filter 16 eliminates noise from output signal S17 from DA converter 15, and supplies the resulting signal to adder 17. Adder 17 adds together the value of output signal S19 from loop filter 14 and the value of output signal S18 from low-pass filter 16 and generates control voltage signal (modulation signal) S11, and supplies this signal to voltage controlled oscillator 11.
As adder 17 generates control voltage signal (modulation signal) S11 by combining two modulation components generated in this way, and supplies this signal to voltage controlled oscillator 11, wideband modulation is implemented.
FIG. 2 is a drawing for explaining the frequency characteristics of a wideband PLL modulation circuit. Here, the PLL transfer function is designated H(s) (where s=jΩ). H(s) has the kind of low-pass characteristic shown in FIG. 2. A low-pass filter with transfer function H(s) is applied to a modulation signal applied to the division ratio set in divider 12. On the other hand, a high-pass filter with the kind of transfer function {1−H(s)} shown in FIG. 2 is applied to a modulation signal applied to the control voltage terminal of voltage controlled oscillator 11.
As these two modulation components are added by adder 17 at the control voltage terminal of voltage controlled oscillator 11, the modulation signal is supplied to voltage controlled oscillator 11 with the flat characteristic shown by the dotted line in FIG. 2 equivalently applied. As a result, it is possible to output a wideband RF modulation signal that extends beyond the PLL band.
Factors that affect the modulation accuracy of two-point modulation will now be described.
Factors that lower modulation accuracy are voltage controlled oscillator 11 control sensitivity (hereinafter referred to as “control sensitivity”) mismatching and control sensitivity nonlinearity.
First, control sensitivity mismatching will be explained.
Degradation of modulation accuracy due to control sensitivity mismatching occurs when the amplitude of a signal output from DA converter 15 and the control sensitivity of voltage controlled oscillator 11 do not match. Control sensitivity denotes conversion gain when the amplitude of a modulation signal input to the control voltage terminal of voltage controlled oscillator 11 is converted to a frequency shift of RF modulation signal S12 output from voltage controlled oscillator 11. The unit of control sensitivity is [Hz/V].
If the control sensitivity does not match, transfer function {1−H(s)} fluctuates as shown in FIG. 3. FIG. 3 shows a transfer function when transfer function {1−H(s)} is multiplied by an a-fold deviation amount. That is to say, the combined characteristic of H(s) and {1−H(s)} is no longer flat gain, as shown by the dotted line in FIG. 3. This is a factor in the degradation of modulation accuracy.
As a way of countering this problem, a method has been devised whereby a control sensitivity table is prepared for per-LSI control sensitivity due to element value variation, and matching of modulation signal amplitude and control sensitivity is achieved according to the oscillation frequency (see Patent Document 2, for example). By means of this method, degradation of modulation accuracy when control sensitivity fluctuates can be suppressed.
Next, control sensitivity nonlinearity will be explained.
Thus far, control sensitivity has been described as a straight line whose slope differs according to the oscillation frequency. In a system that handles a narrowband modulation signal, there is no problem if this control sensitivity is treated approximately as a straight line.    Patent Document 1: U.S. Pat. No. 4,308,508 specification    Patent Document 2: U.S. Pat. No. 6,211,647 specification